As shown in FIG. 16, a semiconductor logic circuit is shipped through three stages, which are designing, manufacturing and testing stages. In the testing stage, a test vector, wherein the logic value of each logic bit is determined as either 0 or 1, is applied to the manufactured semiconductor logic circuit, and a test response from the semiconductor logic circuit is observed and compared to an expected test response, so that it is judged if the circuit is defective or non-defective. A ratio by which the non-defective products can be obtained is called the yielding percentage, and the yielding percentage largely affects the quality, reliability and manufacturing costs of the semiconductor logic circuit.
In general, the manufactured semiconductor logic circuit is mostly a sequential circuit. The sequential circuit comprises a combinational circuit unit including one or a plurality of AND gates, one or a plurality of NAND gates, one or a plurality of OR gates, one or a plurality of NOR gates and the like, and flip-flops for memorizing internal states of the circuit. Hereupon, the combinational circuit unit comprises an external input wire (primary input:PI), a pseudo external input wire (pseudo primary input:PPI) which is an output wire of the flip-flop, an external output wire (primary output:PO), and a pseudo external output wire (pseudo primary output:PPO) which is an input wire of the flip-flop. Inputs to the combinational circuit unit include those directly supplied from the external input wire and those supplied via the pseudo external input wire. Outputs from the combinational circuit unit include those appearing on the external output wire directly and those appearing on the pseudo external output wire.
In order to test the combinational circuit unit of the sequential circuit, it is necessary to apply a required test vector from the external input wire and the pseudo external input wire of the combinational circuit unit and observe a test response from the external output wire and the pseudo external output wire of the combinational circuit unit. Bits corresponding to the external input wire and the pseudo external input wire constitute one test vector, and bits corresponding to the external output wire and the pseudo external output wire constitute one test response.
However, in general, the output wire (pseudo external input wire) and the input wire (pseudo external output wire) of the flip-flop of the sequential circuit cannot be directly accessed from outside. Therefore, there are problems in the controllability of the pseudo external input wire and the observability of the pseudo external output wire when the combinational circuit unit is tested.
A method of solving the problems described above in the controllability and observability in the test of the combinational circuit unit which is mostly adopted is the full scan design. Describing the full scan design, the flip-flops are replaced with scan flip-flops, and the scan flip-flops are used to form one or a plurality of scan chains. The operation of the scan flip-flops is controlled by a scan enable (SE) signal wire. For example, when SE=0, the operation of the scan flip-flops is the same as that of the conventional flip-flops, and output values of the scan flip-flops are updated by a value from the combinational circuit unit when a clock pulse is given thereto. When SE=1, the scan flip-flop and another scan flip-flop in the same scan chain form one shift register, and new values are shifted into the scan flip-flops from outside and current values in the scan flip-flops are shifted out therefrom when the clock pulse is given thereto. The scan flop-flops in the same scan chain conventionally share the same scan enable (SE) signal wire, however, the scan flop-flips in the different scan chains may share the same scan enable (SE) signal wire or may respectively use different ones.
The combinational circuit unit of the full scan sequential circuit is tested in such a manner that scan shift and scan capture are repeated. The scan shift is performed in shift mode wherein the scan enable (SE) signal wire is set to logic value 1. In the shift mode, one or a plurality of clock pulses is given, and one or a plurality of new values is shifted into the scan flip-flops in the scan chain from outside, and, at the same time, one or a plurality of current values in the scan flip-flops in the scan chain is shifted out therefrom. The scan capture is performed in capture mode wherein the scan enable (SE) signal wire is set to logic value 0. In the capture mode, one clock pulse is simultaneously given to all of the scan flip-flops in one scan chain, and a value of the pseudo external output wire in the combinational circuit unit is fetched into all of the scan flip-flops.
The scan shift is used in order to apply the test vector to the combinational circuit unit via the pseudo external input wire and observe the test response from the combinational circuit unit via the pseudo external output wire. Further, the scan capture is used to fetch the test response from the combinational circuit unit into the scan flip-flops. All of the test vectors are subjected to the scan shift and the scan capture so that the combinational circuit unit can be tested. Such a test method is called the scan test method.
In the scan test method, the test vector may be applied to the combinational circuit unit directly via the external input or by means of the scan shift. Because an arbitrary logic value can be set in an arbitrary scan flip-flop by the scan shift, the problem in the controllability of the pseudo external input wire can be solved. The observation of the test response from the combinational circuit unit may be performed directly via the external output or by means of the scan shift. Because the output value of the arbitrary scan flip-flop can be observed by means of the scan shift, the problem in the observability of the pseudo external output wire can be solved. As described, it is only required in the scan test method to obtain the test vector and the expected test response using an automatic test pattern generation (ATPG) program.
The scan test method described above, which is a very effective means, still includes the problem that more power is consumed in the test than in a normal operation. In the case where a CMOS circuit constitutes a semiconductor logic circuit, the power consumption includes static power consumption due to leak current and dynamic power consumption due to the switching activity of logic gates and flip-flops. Further, the latter power consumption, which is the dynamic power consumption, includes shift power consumption in a shift operation and capture power consumption in a capture operation.
A large number of clock pulses are conventionally given to one test vector at the time of the scan shift. For example, it is necessary to supply as many clock pulses as the number of the scan flip-flops at maximum in order to set new values in all of the scan flip-flops in one scan chain. Therefore, the shift power consumption is thereby increased, which may cause excessive heat generation. The excessive heat generation may lead to the breakage of the semiconductor logic circuit. Therefore, a method of reducing the shift power consumption has been actively studied.
The number of the clock pulses necessary for one test vector at the time of the scan capture is conventionally one for one scan chain. Therefore, the heat generation resulting from the scan capture power consumption does not present any problem. However, if there is a difference between the test response value and the current value of the scan flip-flop when the test response of the combinational circuit unit appearing on the pseudo external output wire is fetched into the scan flip-flop in the capture mode, the output value of the corresponding scan flip-flop changes. In the case where there is a large number of scan flip-flops which thus change the output values, a power supply voltage tentatively drops due to the switching activity of the logic gates and the scan flip-flops, which is called the IR (I: current, R: resistance) drop. The IR drop may result the malfunction of the circuit, as a result of which a wrong test value may be fetched into the scan flip-flop. Accordingly, the semiconductor logic circuit normally operable in a normal operation, may be wrongly judged to be a defective product when tested. As a result, the yielding percentage is deteriorated. In the case where the semiconductor logic circuit achieves a large scale, ultra-miniaturization and lower power supply voltage, the yielding loss induced by the false test is evident. Therefore, it is necessary to reduce the capture power consumption.
In the case where a single clock is used in the test, the scan capture power consumption can be reduced by means of the clock gating method, which, however, largely affects the physical design of the semiconductor logic circuit. In the case where a multiple clock signal is used in the test, the scan capture power consumption can be reduced by means of the one-hot method or multiple clock method. However, a test data volume is significantly increased in the first, while an enormous amount of memory consumption is necessary for the generation of the test vector in the latter, which both impose a significant burden on the ATPG. In the process of reducing the scan capture power consumption, it is desirable to lessen the influence on the physical design, the increase of the test data volume and the burden on the ATPG.
A test cube including don't care bits, that is, a logic bit which can be either the logic value 0 or the logic value 1 for achieving a predetermined object, is often generated in the process where the test vector is generated according to the ATPG program. In contrast, a test input not including the don't care bits but only includes logic bits (bits having the logic value 0 or logic value 1) is called a test vector. In the case where a test vector set not including the don't care bits is supplied, a part of the bits of a part of the test vectors can be set as the don't care bits without any change to a fault coverage of the set. In other words, the test cube can be obtained by a don't care bit specified program. The test cube is present because one or a plurality of targeted faults in the combinational circuit unit of the full scan sequential circuit can be often detected when the necessary logic values are simply set in a part of the bits in the external input wire and the pseudo external input wire. Though 0 or 1 is set in the rest of the bits, the detection of the targeted faults is not thereby influenced. Therefore, such influence-free bits are the don't care bits for the targeted faults.
The Non-Patent Documents 1 through 3 recite the technologies wherein a part of bits of a part of test vectors is changed into the don't care bits in a test vector set not including the don't care bits without any change to a fault coverage thereof.
The Non-Patent Document 1 recites the method of sequentially checking if respective bits called Bit-Striping can be the don't care bits in order to identify the don't care bit in each test vector. This method completely ignores a correlative relationship between the test vectors, and further, is disadvantageous in that a processing time is longer in proportion to the number of the bits.
The Non-Patent Document 2 recites the discrimination of the don't care bit based on the method called XID. This technology is different to that of the Non-Patent Document 1 in that, not each of the test vectors is independently processed, but all of the test vectors in the given test vector set are simultaneously processed in the XID method. More specifically, any fault which can only be detected by each test vector (essential fault) is detected. Then, the implication operation and logical justification of the ATPG the logic are applied so that values to be set necessarily for the detection of all of the essential faults are obtained. As a result, the other logic bits are set as the don't care bits. The method, wherein all of the input bits are not simulated, can achieve an improved efficiency and a higher speed in its execution time than the method proposed in the Non-Patent Document 1 described earlier. However, the relevant don't care bit method is not subjected to constraint conditions, meaning that any logic bit can be possibly set as the don't care bit.
In the Non-Patent Document 3, all of the test vectors in the given test vector set are simultaneously processed in place of each of the test vectors being independently processed in a manner similar to the technology recited in the Non-Patent Document 2 described earlier. A technical difference between the Non-Patent Documents 2 and 3 is that it is not allowed that any logic bit is set as the don't care bit, and the don't care bits are identified from only a part of the logic bits (called candidate bits). The don't care bit is not identified from any logic bit (called fixed bit) other than the candidate bits. In the Non-Patent Document 3, the don't care bit is identified under constraint conditions which are composed of the candidate bits and the fixed bits. This technology is advantageous in that a high speed can be achieved in a manner similar to that of the Non-Patent Document 2 described earlier, and the don't care bit can be efficiently identified so that a predetermined object can be achieved. Such an efficiency in achieving the object obviously relates to the positions of the don't care bits, therefore, it is important to set the constraint conditions including the candidate bits and fixed bits in compliance with the object.
The test cube including the don't care bits is, after all, an intermediate object appearing in the process of generating the test vector not including the don't care bits. Therefore, it is necessary to finally embed the logic value 0 or 1 in the don't care bits in the test cube.
When the logic value 0 or 1 is embedded, the necessary logic value (0 or 1) for achieving some object is conventionally determined for the don't care bits. The Non-Patent Document 4 recites the technology wherein the logic value is determined for the don't care bits of the test cube in order to reduce the scan capture power consumption.
It is recited in the Non-Patent Document 4 that, in the combinational circuit unit of the full scan sequential circuit, the test cube including the don't care bits obtained through various methods is subjected to the three-valued (logic value 0, logic value 1, and X representing don't care bit) simulation so that the test response with respect to the test cube is obtained. Then, bit pairs each provided with a pseudo input wire bit and a pseudo output wire bit are classified into a type-A bit pair including the don't care bit only in the pseudo input wire bit, a type-B bit pair including the don't care bit only in the pseudo output wire bit or a type-C bit par including the don't care bit in both of the pseudo input wire bit and the pseudo output wire bit. Further, these bit pairs are each processed in order. In the processing, the logic value of the corresponding pseudo output wire bit is allocated to the don't care bit of the pseudo input wire bit in the case of the type-A bit pair, the justification operation is performed so that the logic value of the corresponding pseudo input wire bit appears in the don't care bit of the pseudo output wire bit, and the logic value of the don't care bit in the test cube is determined in the case of the type-b bit pair, and the logic value is allocated to the pseudo input wire and the pseudo output wire is justified so that the same logic value (0 or 1) appears in the don't care bits in both of the pseudo input wire bit and the pseudo output wire bit so that the logic value of the don't care bit in the test cube is determined in the case of the type-C bit pair. The embedding technology recited in the Non-Patent Document 4 obviously focus on only one bit pair provided with one pseudo input wire bit and one pseudo output wire bit is regarded in determining the logic value for the don't care bits of the test cube. The logic value thus determined is not always optimal on the whole.
Non-Patent Document 1: R. Sankaralingam and N. A. Touba, “Controlling Peak Power During a Scan Testing”, Proceedings of IEEE VLSI Test Symposium, pp. 153-159, 202.
Non-Patent Document 2: K. Miyase and S. Kajihara, “XID Don't Care Identification of Test Patterns for Combinational Circuits,” IEEE Transactions on Computer-Aided Design, Vol. 23, pp. 321-326, 2004.
Non-Patent Document 3: K. Miyase, S. Kajihara, I. Pomeranz, and S. Reddy, “Don't Care Identification on Specific Bits of Test Patterns,” Proceedings of IEEE/ACM International Conference on Computer Design, pp. 194-199, 2002.
Non-Patent Document 4: X. Wen, H. Yamashita, S. Kajihara, L.-T. Wang, K. Saluja, and K. Kinoshita, “On Low-Capture-Power Test Generation for Scan Testing,” Proceedings of IEEE VLSI Test Symposium, pp. 265-270, 2005.